Micron Technology Turbofan Manual do Utilizador

SDR SDRAMMT48LC2M32B2 – 512K x 32 x 4 BanksFeatures• PC100-compliant• Fully synchronous; all signals registered on positiveedge of system clock• Inter

Figure 3: 90-Ball VFBGA (Top View) 1 2 3 4 6 7 8 95DQ26DQ28VSSQVSSQVDDQVSSA4A7CLKDQM1VDDQVSSQVSSQDQ11DQ13DQ24VDDQDQ27DQ29DQ31DQM3A5A8CKENUDQ8DQ10DQ12V

Table 4: Pin and Ball DescriptionsSymbol Type DescriptionCLK Input Clock: CLK is driven by the system clock. All SDRAM input signals are sampled on th

Package DimensionsFigure 4: 86-Pin Plastic TSOP II (400 mil) – Package Codes TG/P See Detail A2X R 1.002X R 0.750.50TYP0.6110.16 ±0.080.50 ±0.1011.7

Figure 5: 90-Ball VFBGA (8mm x 13mm) – Package Codes B5 Ball A1 ID1.00 MAXMold compound: Epoxy novolacSubstrate material: Plastic laminateSolder bal

Temperature and Thermal ImpedanceIt is imperative that the SDRAM device’s temperature specifications, shown in Temper-ature Limits below, be maintaine

Table 6: Thermal Impedance Simulated ValuesDieRevision Package SubstrateΘJA (°C/W)Airflow =0m/sΘJA (°C/W)Airflow =1m/sΘJA (°C/W)Airflow =2m/s ΘJB (°C/

Figure 7: Example: Temperature Test Point Location, 90-Ball FBGA (Top View) Test point6.50mm13.00mm4.00mm8.00mm64Mb: x32 SDRAMTemperature and Thermal

Electrical SpecificationsStresses greater than those listed may cause permanent damage to the device. This is astress rating only, and functional oper

Table 9: CapacitanceNote 1 applies to all parameters and conditionsPackage Parameter Min Max UnitTSOP Package Input capacitance: CLK 2.5 4.0 pFInput c

Electrical Specifications – IDD ParametersTable 10: IDD Specifications and Conditions – Revision GNotes 1–5 apply to all parameters and conditions; VD

Table 2: Address TableParameter 2 Meg x 32Configuration 512K x 32 x 4 banksRefresh count 4KRow addressing 2K A[10:0]Bank addressing 4 BA[1:0]Column ad

Table 11: IDD Specifications and Conditions – Revision JNotes 1–5 apply to all parameters and conditions; VDD, VDDQ = 3.3V ±0.3VParameter/Condition Sy

Electrical Specifications – AC Operating ConditionsTable 12: Electrical Characteristics and Recommended AC Operating ConditionsNotes 1–5 apply to all

Table 12: Electrical Characteristics and Recommended AC Operating Conditions (Continued)Notes 1–5 apply to all parameters and conditions; VDD, VDDQ =

up simultaneously. VSS and VSSQ must be at same potential.) The two AUTO REFRESHcommand wake-ups should be repeated any time the tREF refresh requirem

Functional DescriptionIn general, this 64Mb SDRAM device (512K x 32x 4 banks) is a quad-bank DRAM thatoperates at 3.3V and include a synchronous inter

CommandsThe following table provides a quick reference of available commands, followed by awritten description of each command. Additional Truth Table

NO OPERATION (NOP)The NO OPERATION (NOP) command is used to perform a NOP to the selected device(CS# is LOW). This prevents unwanted commands from bei

READThe READ command is used to initiate a burst read access to an active row. The valueson the BA0 and BA1 inputs select the bank; the address provid

WRITEThe WRITE command is used to initiate a burst write access to an active row. The valueson the BA0 and BA1 inputs select the bank; the address pro

PRECHARGEThe PRECHARGE command is used to deactivate the open row in a particular bank orthe open row in all banks. The bank(s) will be available for

ContentsGeneral Description ...

REFRESHAUTO REFRESHAUTO REFRESH is used during normal operation of the SDRAM and is analogous toCAS#-BEFORE-RAS# (CBR) refresh in conventional DRAMs.

Truth TablesTable 15: Truth Table – Current State Bank n, Command to Bank nNotes 1–6 apply to all parameters and conditionsCurrent State CS# RAS# CAS#

Read with auto precharge enabled: Starts with registration of a READ commandwith auto precharge enabled and ends when tRP has been met. After tRP is m

Table 16: Truth Table – Current State Bank n, Command to Bank mNotes 1–6 apply to all parameters and conditionsCurrent State CS# RAS# CAS# WE# Command

Read with auto precharge enabled: Starts with registration of a READ commandwith auto precharge enabled and ends when tRP has been met. After tRP is m

Table 17: Truth Table – CKENotes 1–4 apply to all parameters and conditionsCurrent State CKEn-1CKEnCommandnActionnNotesPower-down L L X Maintain power

InitializationSDRAM must be powered up and initialized in a predefined manner. Operational proce-dures other than those specified may result in undefi

Note:More than two AUTO REFRESH commands can be issued in the sequence. After steps 9and 10 are complete, repeat them until the desired number of AUTO

Mode RegisterThe mode register defines the specific mode of operation, including burst length (BL),burst type, CAS latency (CL), operating mode, and w

Figure 13: Mode Register Definition M3 = 01248ReservedReservedReservedFull PageM3 = 11248ReservedReservedReservedReservedOperating Mode Standard Opera

List of FiguresFigure 1: 2 Meg x 32 Functional Block Diagram ...

Burst LengthRead and write accesses to the device are burst oriented, and the burst length (BL) isprogrammable. The burst length determines the maximu

Table 18: Burst Definition TableBurst Length Starting Column AddressOrder of Accesses Within a BurstType = Sequential Type = Interleaved2 A0 0

CAS LatencyThe CAS latency (CL) is the delay, in clock cycles, between the registration of a READcommand and the availability of the output data. The

Bank/Row ActivationBefore any READ or WRITE commands can be issued to a bank within the SDRAM, arow in that bank must be opened. This is accomplished

READ OperationREAD bursts are initiated with a READ command, as shown in Figure 9 (page 27). Thestarting column and bank addresses are provided with t

Figure 16: Consecutive READ BurstsDon’t CareCLKDQDOUT nT2T1 T4T3 T6T5T0CommandAddressREAD NOP NOP NOP NOPBank,Col nNOPBank,Col bDOUTn + 1DOUTn + 2DOUT

Figure 17: Random READ AccessesCLKDQT2T1 T4T3 T6T5T0CommandAddressDon’t CareDOUTDOUTDOUTDOUTCLKDQT2T1 T4T3 T5T0CommandAddressREAD NOPBank,Col nREAD RE

The DQM signal must be de-asserted prior to the WRITE command (DQM latency iszero clocks for input buffers) to ensure that the written data is not mas

Figure 19: READ-to-WRITE With Extra Clock CycleDon’t CareREAD NOP NOPNOP NOPDQMCLKDQDOUTT2T1 T4T3T0CommandAddressBank,Col nWRITEDINBank,Col bT5tDStHZT

Continuous-page READ bursts can be truncated with a BURST TERMINATE commandand fixed-length READ bursts can be truncated with a BURST TERMINATE comman

Figure 51: Clock Suspend Mode ...

Figure 22: Alternating Bank Read Accesses Don’t Care UndefinedEnable auto prechargetCHtCLtCKtACtLZCLKDQA10tOHDOUTtCMHtCMStAHtAStAHtAStAHtASRowRowRowRo

Figure 23: READ Continuous Page Burst tCHtCLtCKtACtLZtRCD CAS latencyCKECLKDQA10tOHDOUTtCMHtCMStAHtAStAHtAStACtOHDOUTRowRowtHZtACtOHDOUTtACtOHDOUTtACt

Figure 24: READ – DQM Operation tCHtCLtCKtACtACtLZtRCD CL = 2 CKECLKDQA10tOHDOUTtCMHtCMStAHtAStAHtAStAHtASRowBankRowBanktHZtACtLZtOHDOUTtOHDOUTtHZComm

WRITE OperationWRITE bursts are initiated with a WRITE command, as shown in Figure 10 (page 28).The starting column and bank addresses are provided wi

Figure 26: WRITE-to-WRITECLKDQT2T1T0CommandAddressNOPWRITE WRITEBank,Col nBank,Col bDINDINDINDon’t CareTransitioning dataNote:1. DQM is LOW. Each WRIT

Figure 27: Random WRITE CyclesDon’t CareCLKDQDINT2T1 T3T0CommandAddressWRITEBank,Col nDINDINDINWRITE WRITE WRITEBank,Col aBank,Col xBank,Col mTransiti

Figure 29: WRITE-to-PRECHARGEDon’t CareDQMCLKDQT2T1 T4T3T0CommandAddressBank a,Col nT5NOPWRITEPRECHARGENOPNOPDINDINACTIVEtRPBank(a or all)tWRBank a,Ro

Figure 30: Terminating a WRITE BurstDon’t CareCLKDQT2T1T0CommandAddressBank,Col nWRITEBURSTTERMINATENEXTCOMMANDDINAddressDataTransitioning dataNote:1.

Figure 31: Alternating Bank Write Accesses Don’t CareEnable auto prechargetCHtCLtCKCLKDQA10tCMHtCMStAHtAStAHtAStAHtASRowRowRowRowCommandtCMHtCMSNOP NO

Figure 32: WRITE – Continuous Page Burst tCHtCLtCKtRCDCKECLKA10tCMStAHtAStAHtASRowRowFull-page burstdoes not self-terminate.Use BURST TERMINATE comman

List of TablesTable 1: Key Timing Parameters ...

Figure 33: WRITE – DQM Operation Don’t CaretCHtCLtCKtRCDCKECLKDQA10tCMStAHtASRowBankRowBankEnable auto prechargeDINtDHtDSDINDINtCMHCommandNOPNOPNOPACT

PRECHARGE OperationThe PRECHARGE command (see Figure 11 (page 29)) is used to deactivate the open rowin a particular bank or the open row in all banks

istered. The last valid data WRITE to bank n will be data registered one clock prior to aWRITE to bank m (see Figure 41 (page 68)).Figure 34: READ Wit

Figure 35: READ With Auto Precharge Interrupted by a WRITE CLKDQDOUTT2T1 T4T3 T6T5T0CommandNOPNOPNOPNOPDINDINDINDIN NOPT7Bank nBank mAddressIdleNOPDQM

Figure 36: READ With Auto Precharge tCHtCLtCKtACtLZtRPtRAStRCD CL = 2 tRCCKECLKDQA10tOHDOUT mtCMHtCMStAHtAStAHtAStAHtASRowRowBankBankRowRowBanktHZtOHD

Figure 37: READ Without Auto Precharge tCHtCLtCKtACtLZtRPtRAStRCD CL = 2 tRCCKECLKDQA10tOHDOUTtCMHtCMStAHtAStAHtAStAHtASRowRowBankBank(s)Bank RowRowBa

Figure 38: Single READ With Auto Precharge tCHtCLtCKtACtOHtLZtRPtRAStRCD CL = 2 tRCCKECLKDQA10DOUTtCMHtCMStAHtAStAHtAStAHtASRowRowBank BankRowRowBankC

Figure 39: Single READ Without Auto Precharge All bankstCHtCLtCKtACtLZtRPtRAStRCD CL = 2tRCCKECLKDQA10tOHDOUTtCMHtCMStAHtAStAHtAStAHtASRowRowBankBank(

Figure 40: WRITE With Auto Precharge Interrupted by a READ Don’t CareCLKDQT2T1 T4T3 T6T5T0CommandWRITE - AP Bank nNOPNOPNOPNOPDINDINNOP NOPT7Bank nBan

Figure 42: WRITE With Auto Precharge Enable auto prechargetCHtCLtCKtRPtRAStRCDtRCCKECLKDQA10tCMHtCMStAHtASRowBank RowBanktWR Don’t CareDINtDHtDSDINDI

General DescriptionThe 64Mb SDRAM is a high-speed CMOS, dynamic random-access memory containing67,108,864 bits. It is internally configured as a quad-

Figure 43: WRITE Without Auto Precharge Disable auto prechargeAll bankstCHtCLtCKtRPtRAStRCDtRCCKECLKDQA10tCMHtCMStAHtASRowBankBankRowBanktWR Don’t Ca

Figure 44: Single WRITE With Auto Precharge Enable auto prechargetCHtCLtCKtRPtRAStRCDtRCCKECLKDQA10tCMHtCMStAHtASRowBank RowBanktWR Don’t CareDINtDHt

Figure 45: Single WRITE Without Auto Precharge tCHtCLtCKtRPtRAStRCDtWRtRCCKECLKDQA10tCMHtCMStAHtAStAHtAStAHtASRowBankBank Bank RowRowBankCommandtCMHtC

AUTO REFRESH OperationThe AUTO REFRESH command is used during normal operation of the device to refreshthe contents of the array. This command is nonp

Figure 46: Auto Refresh Mode All banksDon’t CaretCHtCLtCKCKECLKDQtRFC()()()()tRP()()()()CommandtCMHtCMSNOPNOP()()()()BankACTIVEAUTO REFRESH()()()()NOP

SELF REFRESH OperationThe self refresh mode can be used to retain data in the device, even when the rest of thesystem is powered down. When in self re

Figure 47: Self Refresh Mode All bankstCHtCLtCKtRPCKECLKDQEnter self refresh modePrecharge allactive bankstXSRCLK stable prior to exiting self refresh

Power-DownPower-down occurs if CKE is registered LOW coincident with a NOP or COMMAND IN-HIBIT when no accesses are in progress. If power-down occurs

Clock SuspendThe clock suspend mode occurs when a column access/burst is in progress and CKE isregistered LOW. In the clock suspend mode, the internal

Figure 50: Clock Suspend During READ Burst Don’t CareCLKDQDOUTT2T1 T4T3 T6T5T0CommandAddressREAD NOP NOP NOPBank,Col nNOPDOUTDOUTDOUTCKEInternalclockN

Functional Block DiagramsFigure 1: 2 Meg x 32 Functional Block Diagram 11RAS#CAS#CLKCS#WE#CKE8A[10:0],BA[1:0]DQM[3:0]13256(x32)8192I/O GATINGDQM MASK

Figure 51: Clock Suspend Mode tCHtCLtCKtACtLZDQMCLKDQA10tOHDOUTtAHtAStAHtAStAHtASBanktDHDINtACtHZDOUTCommandtCMHtCMSNOPNOP NOP NOPNOPREAD WRITEDon’t C

Pin and Ball Assignments and DescriptionsFigure 2: 86-Pin TSOP (Top View) VDDDQ0VDDQDQ1DQ2VSSQDQ3DQ4VDDQDQ5DQ6VSSQDQ7NCVDDDQM0WE#CAS#RAS#CS#NCBA0BA1A1